A NEW ARCHITECTURE FOR LOW POWER ROW BYPASSING MULTIPLIER USING RCA

Abstract

 In this paper a new technique for the architecture of the bypassing multiplier for low power and 
high speed is introduced. The basic idea is to bypass blocks of logic when their function is not required, using 
low delay and area overhead components using TG gates. While this technique offers great dynamic power 
savings mainly in array multipliers, due to their regular interconnection scheme, it misses the reduced area 
and fast speed advantages of tree multipliers. 8x8 Row bypassing multiplier is divided into two 8x4 and 4x8, 
when these are combined at middle of the final adder compressor is used to enhance the speed of the row 
bypassing multiplier. HSPICE is used to evaluate the performance of the multiplier for 130 nm at 1.8 Volts.